patch-2.3.9 linux/arch/mips/kernel/head.S

• Lines: 284
• Date: Fri Jun 25 17:40:12 1999
• Orig file: v2.3.8/linux/arch/mips/kernel/head.S
• Orig date: Tue Oct 20 13:52:54 1998

diff -u --recursive --new-file v2.3.8/linux/arch/mips/kernel/head.S linux/arch/mips/kernel/head.S
@@ -1,4 +1,4 @@
-/* $Id: head.S,v 1.13 1998/10/14 20:26:27 ralf Exp $
+/* $Id: head.S,v 1.11 1998/10/18 13:27:12 tsbogend Exp $
  *
  * arch/mips/kernel/head.S
  *
@@ -408,15 +408,7 @@
 
 probe_done:
 
-#ifndef CONFIG_SGI
-	/* Get the memory upper limit the bootloader passed to us
-	 * in a0
-	 */
-	la	t0, mips_memory_upper
-	nop
-	sw	a0, (t0)		
-#else
-	/* On SGI's the firmware/bootloader passes argc/argp/envp
+	/* The firmware/bootloader passes argc/argp/envp
 	 * to us as arguments.  But clear bss first because
 	 * the romvec and other important info is stored there
 	 * by prom_init().
@@ -431,6 +423,7 @@
 
 	jal	prom_init /* prom_init(argc, argv, envp); */
 	 nop
+#ifdef CONFIG_SGI
 	jal	sgi_sysinit
 	 nop
 #endif
@@ -440,18 +433,6 @@
 	 nop
 #endif
 
-	/* Get the very one tags we need early in the boot process */
-	nop
-	jal	bi_EarlySnarf
-	 nop
-#ifndef CONFIG_SGI
-	/* Clear BSS first so that there are no surprises... */
-	la	t0, _edata
-	la	t1, _end
-1:	addiu	t0, 1
-	bne	t0, t1, 1b
-	sb	zero, -1(t0)
-#endif
 	/*
 	 * Determine the mmu/cache attached to this machine,
 	 * then flush the tlb and caches.  On the r4xx0
@@ -460,34 +441,10 @@
 	jal	loadmmu
 	 nop
 
-	la	t2, mips_cputype
-	lw	t4, (t2)
-	li	t1, CPU_R2000
-	li	t2, CPU_R3000
-	li	t3, CPU_R3000A
-	beq	t4,t1,2f
-	 nop		
-
-	beq	t4,t2,2f
-	 nop		
-
-	beq	t4,t3,2f
-	 nop		
-
-	jal	wire_mappings_r4xx0
-	 nop	
-
-	b	9f
-	 nop
-
-2:
-	jal	wire_mappings_r3000
-	 nop	
-
 	/*
 	 * Stack for kernel and init, current variable
 	 */
-9:	la	$28, init_task_union
+	la	$28, init_task_union
 	addiu	t0, $28, KERNEL_STACK_SIZE-32
 	sw	t0, kernelsp
 	subu	sp, t0, 4*SZREG
@@ -509,81 +466,6 @@
 	 nop					# delay slot
 	END(kernel_entry)
 
-/*
- * wire_mappings - used to map hardware registers, r4xx0 version.
- */
-LEAF(wire_mappings_r4xx0)
-	mtc0	zero, CP0_WIRED
-	nop
-	nop
-	nop
-	j	ra
-	 nop
-	END(wire_mappings_r4xx0)
-
-/*
- * R3000 version of wire_mappings.
- */
-LEAF(wire_mappings_r3000)
-	/*
-	 * Get base address of map0 table for the
-	 * the board we're running on
-	 */
-	lw	t1, mips_machtype
-	la	t0, map0table
-	sll	t1, PTRLOG		# machtype used as index
-	addu	t0, t1
-	lw	t0, (t0)		# get base address
-	nop
-	/* Get number of wired TLB entries and
-	 * loop over selected map0 table.
-	 */
-	lw	t1, (t0)		# number of wired TLB entries
-	move	t2, zero		# TLB entry counter
-	addiu	t3, t1, 1		# wire one additional entry
-	beqz	t1, 2f			# null, exit
-	 nop
-
-	addiu	t0, 8
-1:
-	lw	t4, 24(t0)		# PageMask
-	ld	t5,  0(t0)		# entryHi
-	ld	t6,  8(t0)		# entryLo0
-	addiu	t2, 1			# increment ctr
-	mtc0	t2, CP0_INDEX		# set TLB entry
-	nop
-	mtc0	t5, CP0_ENTRYHI
-	nop
-	mtc0	t6, CP0_ENTRYLO0
-	addiu	t0, 32
-	bne	t1, t2, 1b		# next TLB entry
-	 tlbwi
-
-	/* We use only 4k pages. Therefore the PageMask register
-	 * is expected to be setup for 4k pages.
-	 */
-2:
-	/* Now map the pagetables */
-	mtc0	zero, CP0_INDEX
-	la	t0, TLB_ROOT
-	mtc0	t0, CP0_ENTRYHI
-	nop
-	la	t0, swapper_pg_dir
-	srl	t0, 12
-	ori	t0, (0x00e0|0x0100)	# uncachable, dirty, valid
-	mtc0	t0, CP0_ENTRYLO0
-	nop
-	tlbwi				# delayed
-
-	/* Load the context register with zero.  To see why, look
-	 * at how the tlb refill code above works.
-	 */
-	mtc0	zero, CP0_CONTEXT
-
-	jr	ra
-	 nop
-	END(wire_mappings_r3000)
-
 	/* CPU type probing code, called at Kernel entry. */
 	LEAF(cpu_probe)
 	mfc0	t0, CP0_PRID
@@ -707,115 +589,6 @@
 	b	probe_done
 	 nop
 	END(cpu_probe)
-
-	.data
-/*
- * Build an entry for table of wired entries
- */
-#define MAPDATA(q1,q2,q3,w1)                                    \
-		.quad	q1;                                     \
-		.quad	q2;                                     \
-		.quad	q3;                                     \
-		.word	w1;                                     \
-		.word	0
-
-/*
- * Initial mapping tables for supported Mips boards.
- * First item is always the number of wired TLB entries,
- * following by EntryHi/EntryLo pairs and page mask.
- * Since everything must be quad-aligned (8) we insert
- * some dummy zeros.
- *
- * Keep in mind that the PFN does not depend on the page size in the
- * TLB page mask register.  See milo's lib/dumptlb.c for how to decode
- * and encode these entries.  Don't see the same routine in the linux
- * kernel distribution, since it is older and unreliable.
- */
-
-/*
- * Address table of mapping tables for supported Mips boards.
- * Add your own stuff here but don't forget to define your
- * target system in bootinfo.h
- */
-
-map0table:	PTR	map0_dummy		# machtype = unknown
-		PTR	map0_rpc		# Deskstation rPC44
-		PTR	map0_tyne		# Deskstation Tyne
-		PTR	map0_pica61		# Acer Pica-61
-		PTR	map0_magnum4000		# MIPS Magnum 4000PC (RC4030)
-		PTR	map0_dummy
-		PTR	map0_dummy		# DEC Personal DECStation 5000/2x (for now)
-		PTR	map0_sni_rm200_pci	# SNI RM200 PCI
-		PTR	map0_dummy		# SGI INDY
-
-map0_dummy:	.word	0			# 0 entries
-
-		.align  3
-/*
- * Deskstation rpc44 mappings.  This machine has its EISA bus at physical
- * address 0xa0000000 which we map for 32M, but that doesn't match EISA
- * spec.  Not sure what to do about this.  Its I/O ports are memory mapped
- * at physical memory location 0xb0000000.
- */
-map0_rpc: 	.word   2			# no. of wired TLB entries
-		.word	0			# pad for alignment
-
-MAPDATA(0xffffffffe0000000, 0x02800017, 0x00000001, PM_16M)	# ISA Memory space
-MAPDATA(0xffffffffe2000000, 0x02c00017, 0x00000001, PM_64K)	# ISA I/O Space
-
-/*
- * Initial mappings for Deskstation Tyne boards.
- */
-map0_tyne: 	.word   2			# no. of wired TLB entries
-		.word	0			# pad for alignment
-
-MAPDATA(0xffffffffe0000000, 0x04020017, 0x00000001, PM_1M)	# VESA DMA cache
-MAPDATA(0xffffffffe2000000, 0x24000017, 0x04000017, PM_16M)	# VESA I/O and memory space
-
-/*
- * Initial mapping for ACER PICA-61 boards.
- * FIXME: These are rather preliminary since many drivers, such as serial,
- * parallel, scsi and ethernet need some changes to distinguish between "local"
- * (built-in) and "optional" (ISA/PCI) I/O hardware. Local video ram is mapped
- * to the same location as the bios maps it to. Console driver has been changed
- * accordingly (new video type: VIDEO_TYPE_PICA_S3).
- * FIXME: Remove or merge some of the mappings.
- */
-map0_pica61:	.word  	7			# no. wired TLB entries
-		.word	0			# dummy
-
-MAPDATA(0xffffffffe0000000, 0x02000017, 0x00000001, PM_64K)	# Local I/O space
-MAPDATA(0xffffffffe0100000, 0x03c00017, 0x00000001, PM_4K)	# Interrupt source register
-MAPDATA(0xffffffffe0200000, 0x01800017, 0x01804017, PM_1M)	# Local video control
-MAPDATA(0xffffffffe0400000, 0x01808017, 0x0180c017, PM_1M)	# Extended video control
-MAPDATA(0xffffffffe0800000, 0x01000017, 0x01010017, PM_4M)	# Local video memory (BIOS mapping)
-MAPDATA(0xffffffffe2000000, 0x02400017, 0x02440017, PM_16M)	# ISA I/O and ISA memory space (both 16M)
-MAPDATA(0xffffffffffffe000, 0x00000001, 0x0001ffd7, PM_4K)	# PCR (???)
-
-/*
- * Initial mapping for Mips Magnum 4000PC systems.
- * Do you believe me now that the Acer and Mips boxes are nearly the same ? :-)
- * FIXME: Remove or merge some of the mappings.
- */
-map0_magnum4000:
-		.word  	8			# no. wired TLB entries
-		.word	0			# dummy
-
-MAPDATA(0xffffffffe1000000, 0x03ffc013, 0x00000001, PM_256K)	# 0
-MAPDATA(0xffffffffe0000000, 0x02000017, 0x00000001, PM_64K)	# 1 local I/O
-MAPDATA(0xffffffffe0100000, 0x03c00017, 0x00000001, PM_4K)	# 2 IRQ source
-MAPDATA(0xffffffffe0200000, 0x01800017, 0x01804017, PM_1M)	# 3 local video ctrl
-MAPDATA(0xffffffffe0400000, 0x01808017, 0x0180c017, PM_1M)	# 4 ext. video ctrl
-MAPDATA(0xffffffffe0800000, 0x01000017, 0x01010017, PM_4M)	# 5 local video mem.
-MAPDATA(0xffffffffe2000000, 0x02400017, 0x02440017, PM_16M)	# 6 ISA I/O and mem.
-MAPDATA(0xffffffffffffe000, 0x00000001, 0x0001ffd7, PM_4K)	# 7 PCR
-
-/*
- * The RM200 doesn't need any wired entries.
- */
-map0_sni_rm200_pci:
-		.word  	0			# no. wired TLB entries
-		.word	0			# dummy
 
 /*
  * This buffer is reserved for the use of the cache error handler.