patch-2.2.14 linux/include/asm-s390/spinlock.h

• Lines: 216
• Date: Tue Jan 4 10:12:24 2000
• Orig file: v2.2.13/linux/include/asm-s390/spinlock.h
• Orig date: Wed Dec 31 16:00:00 1969

diff -u --recursive --new-file v2.2.13/linux/include/asm-s390/spinlock.h linux/include/asm-s390/spinlock.h
@@ -0,0 +1,215 @@
+/*
+ *  include/asm-s390/spinlock.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/spinlock.h"
+ */
+
+#ifndef __ASM_SPINLOCK_H
+#define __ASM_SPINLOCK_H
+
+#ifndef __SMP__
+
+/*
+ * Your basic spinlocks, allowing only a single CPU anywhere
+ *
+ * Gcc-2.7.x has a nasty bug with empty initializers.
+ */
+#if (__GNUC__ > 2) || (__GNUC__ == 2 && __GNUC_MINOR__ >= 8)
+typedef struct { } spinlock_t;
+  #define SPIN_LOCK_UNLOCKED (spinlock_t) { }
+#else
+  typedef struct { int gcc_is_buggy; } spinlock_t;
+  #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
+#endif
+
+#define spin_lock_init(lock)	do { } while(0)
+#define spin_lock(lock)		do { } while(0)
+#define spin_trylock(lock)	do { } while(0)
+#define spin_unlock(lock)	do { } while(0)
+#define spin_lock_irq(lock)	cli()
+#define spin_unlock_irq(lock)	sti()
+
+#define spin_lock_irqsave(lock, flags) \
+	do { save_flags(flags); cli(); } while (0)
+#define spin_unlock_irqrestore(lock, flags) \
+	restore_flags(flags)
+
+/*
+ * Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts
+ * but no interrupt writers. For those circumstances we
+ * can "mix" irq-safe locks - any writer needs to get a
+ * irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ *
+ * Gcc-2.7.x has a nasty bug with empty initializers.
+ */
+#if (__GNUC__ > 2) || (__GNUC__ == 2 && __GNUC_MINOR__ >= 8)
+  typedef struct { } rwlock_t;
+  #define RW_LOCK_UNLOCKED (rwlock_t) { }
+#else
+  typedef struct { int gcc_is_buggy; } rwlock_t;
+  #define RW_LOCK_UNLOCKED (rwlock_t) { 0 }
+#endif
+
+#define read_lock(lock)		do { } while(0)
+#define read_unlock(lock)	do { } while(0)
+#define write_lock(lock)	do { } while(0)
+#define write_unlock(lock)	do { } while(0)
+#define read_lock_irq(lock)	cli()
+#define read_unlock_irq(lock)	sti()
+#define write_lock_irq(lock)	cli()
+#define write_unlock_irq(lock)	sti()
+
+#define read_lock_irqsave(lock, flags)	\
+	do { save_flags(flags); cli(); } while (0)
+#define read_unlock_irqrestore(lock, flags) \
+	restore_flags(flags)
+#define write_lock_irqsave(lock, flags)	\
+	do { save_flags(flags); cli(); } while (0)
+#define write_unlock_irqrestore(lock, flags) \
+	restore_flags(flags)
+
+#else /* __SMP__ */
+
+/* Simple spin lock operations.  There are two variants, one clears IRQ's
+ * on the local processor, one does not.
+ *
+ * We make no fairness assumptions. They have a cost.
+ */
+
+typedef struct {
+	volatile unsigned long lock;
+} spinlock_t;
+
+#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
+#define spin_lock_init(lp) do { (lp)->lock = 0; } while(0)
+#define spin_unlock_wait(lp)	do { barrier(); } while((lp)->lock)
+
+extern inline void spin_lock(spinlock_t *lp)
+{
+	__asm__ __volatile("    lhi   1,-1\n"
+			   "0:  slr   0,0\n"
+			   "    cs    0,1,%1\n"
+			   "    jl    0b"
+			   : "=m" (lp->lock)
+			   : "0" (lp->lock) : "0", "1");
+}
+
+extern inline int spin_trylock(spinlock_t *lp)
+{
+	unsigned long result;
+	__asm__ __volatile("    slr   %1,%1\n"
+			   "    lhi   0,-1\n"
+			   "0:  cs    %1,0,%0"
+			   : "=m" (lp->lock), "=&d" (result)
+			   : "0" (lp->lock) : "0");
+	return !result;
+}
+
+
+
+extern inline void spin_unlock(spinlock_t *lp)
+{
+	__asm__ __volatile("    xc 0(4,%0),0(%0)\n"
+                           "    bcr 15,0"
+			   : /* no output */ : "a" (lp) );
+}
+		
+#define spin_lock_irq(lock) \
+	do { __cli(); spin_lock(lock); } while (0)
+#define spin_unlock_irq(lock) \
+	do { spin_unlock(lock); __sti(); } while (0)
+
+#define spin_lock_irqsave(lock, flags) \
+	do { __save_flags(flags); __cli(); spin_lock(lock); } while (0)
+#define spin_unlock_irqrestore(lock, flags) \
+	do { spin_unlock(lock); __restore_flags(flags); } while (0)
+
+/*
+ * Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts
+ * but no interrupt writers. For those circumstances we
+ * can "mix" irq-safe locks - any writer needs to get a
+ * irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+typedef struct {
+	volatile unsigned long lock;
+	volatile unsigned long owner_pc;
+} rwlock_t;
+
+#define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 }
+
+extern void _read_lock(rwlock_t *rw);
+extern void _read_unlock(rwlock_t *rw);
+extern void _write_lock(rwlock_t *rw);
+extern void _write_unlock(rwlock_t *rw);
+
+#define read_lock(rw)   \
+        asm volatile("   l     2,%0\n"   \
+                     "0: sll   2,1\n"    \
+                     "   srl   2,1\n"     /* clear high (=write) bit */ \
+                     "   lr    3,2\n"    \
+                     "   ahi   3,1\n"     /* one more reader */ \
+                     "   cs    2,3,%0\n"  /* try to write new value */ \
+                     "   jl    0b"       \
+                     : "+m" ((rw)->lock) : : "2", "3" );
+
+#define read_unlock(rw) \
+        asm volatile("   l     2,%0\n"   \
+                     "0: lr    3,2\n"    \
+                     "   ahi   3,-1\n"    /* one less reader */ \
+                     "   cs    2,3,%0\n" \
+                     "   jl    0b"       \
+                     : "+m" ((rw)->lock) : : "2", "3" );
+
+#define write_lock(rw) \
+        asm volatile("   lhi   3,1\n"    \
+                     "   sll   3,31\n"    /* new lock value = 0x80000000 */ \
+                     "0: slr   2,2\n"     /* old lock value must be 0 */ \
+                     "   cs    2,3,%0\n" \
+                     "   jl    0b"       \
+                     : "+m" ((rw)->lock) : : "2", "3" );
+
+#define write_unlock(rw) \
+        asm volatile("   slr   3,3\n"     /* new lock value = 0 */ \
+                     "0: lhi   2,1\n"    \
+                     "   sll   2,31\n"    /* old lock value must be 0x80000000 */ \
+                     "   cs    2,3,%0\n" \
+                     "   jl    0b"       \
+                     : "+m" ((rw)->lock) : : "2", "3" );
+
+#define read_lock_irq(lock)	do { __cli(); read_lock(lock); } while (0)
+#define read_unlock_irq(lock)	do { read_unlock(lock); __sti(); } while (0)
+#define write_lock_irq(lock)	do { __cli(); write_lock(lock); } while (0)
+#define write_unlock_irq(lock)	do { write_unlock(lock); __sti(); } while (0)
+
+#define read_lock_irqsave(lock, flags)	\
+	do { __save_flags(flags); __cli(); read_lock(lock); } while (0)
+#define read_unlock_irqrestore(lock, flags) \
+	do { read_unlock(lock); __restore_flags(flags); } while (0)
+#define write_lock_irqsave(lock, flags)	\
+	do { __save_flags(flags); __cli(); write_lock(lock); } while (0)
+#define write_unlock_irqrestore(lock, flags) \
+	do { write_unlock(lock); __restore_flags(flags); } while (0)
+
+#endif /* SMP */
+#endif /* __ASM_SPINLOCK_H */
+
+
+
+
+
+
+
+
+